In U.S. Pat. No. 4,868,427, incorporated herein by reference, a translator circuit for converting a small-swing ECL-like (Emitter Coupled Logic) signal to a large-swing TTL-like (Transistor-Transistor Logic) signal is shown and described. In the preferred embodiment of the invention of U.S. Pat. No. 4,868,427, shown in FIG. 5 of U.S. Pat. No. 4,868,427 and reproduced as FIG. 1 herein, transistor Q5 is switched on or off depending upon the difference in magnitudes of the voltages applied to input terminals IN and IN. This circuit of FIG. 1 is configured so that the gate-to-source voltage (V.sub.GS) of transistor Q5 is equal to its threshold voltage when the voltages at terminals IN and IN are equal. Thus, a relatively small deviation in the voltages applied to terminals IN and IN should cause the voltage at node 2 to turn transistor Q5 on or off.
In the translator circuit of FIG. 1, ideally, the voltage at node 1 totally controls the current through transistors Q3 and Q4, configured as current mirrors, and the voltage at node 2 should not affect the current through transistor Q4. However, since transistor Q4 is not an ideal transistor but has some output resistance, calculated using the equation .DELTA.V.sub.DS /.DELTA.I.sub.DS, an increased drain voltage at node 2 causes an increased current through transistor Q4, given a fixed V.sub.GS of transistor Q4. This, in turn, causes a greater voltage drop across resistor R2, which causes the voltage at node 2 to undesirably lower at a time when the voltage at node 2 is intended to be raised. Conversely, a change in the voltages of terminals IN and IN which causes the voltage at node 2 to swing low would cause the current through transistor Q4 to decrease and thus undesirably raise the voltage at node 2.
This dependence of the drain-to-source current (I.sub.DS) on the value of the drain-to-source voltage (V.sub.DS) across transistor Q4 reduces the magnitude of the voltage swing at node 2 in response to the difference in voltages applied to input terminals IN and IN. Consequently, this delays the time that transistor Q5, whose control terminal is coupled to node 2, is turned completely on or off and may require higher translator circuit input signal swings to ensure the proper switching of transistor Q5 or to have a sufficient noise margin. Further, this reduced output signal swing requires a more precise tolerance of the various components comprising the translator circuit to ensure that the midpoint of the node 2 swing equals the threshold voltage of transistor Q5 or the threshold voltage of any logic circuit coupled to the output of the translator circuit.
What is needed is an improvement to the circuit of FIG. 1 which makes the current through transistor Q4 substantially totally dependent upon the voltage applied to its gate and not affected by a change of voltage at node 2. This would increase the voltage swing at node 2 and greatly increase the switching speed of a subsequent stage coupled to the translator circuit and improve the reliability of the translator circuit.